Job Title

Synapse Design is looking forward to hire Design Verification Engineer expert.Qualifications, skills, and all relevant experience needed for this role can be found in the full description below.Experience:: +10 yearsRequirements:Solid programming skills in C/C++, Verilog, System Verilog, UVM, assembly, Perl/Python.Proficient in debugging complex SOC or CPU core designs involving multithreading, scheduling.Experience in triaging regressions, debugging, and resolving down to RTL or Testbench issues. Experience building UVM scoreboards for NOC based Switching, Routing networks . Understanding of DFT/X and Post Silicon ATE correlation.Preferred SkillsAbility to create and connect C/C++ reference models via DPI for RTL-to-C checking.Experience with Formal Verification using tools like: Cadence JasperGold, Synopsys VCF or similar.Good understanding of number formats Floating-point arithmetic(FP8,FP16 FP32) and implementation.Knowledgeable in RISCV/ARM assembly programmingGate-level simulation experienceKnowledge of UPF based simulations.If interested, please share your resume at shashank.verma@ and let me know your best time to reach.