OPENEDGES develops AI Edge Computing semiconductor IPs, so that more people can enjoy AI technology closer.Have you got what it takes to succeed The following information should be read carefully by all candidates.???? Location: San Jose, CA, USA or Austin, TX, USA???? Position: Design Verification EngineerOPENEDGES is the world's only total memory system and AI platform IP solution company that has delivered NPU, memory controllers, DDR PHY, and on-chip interconnect IPs all together in one place since 2017.Job Summary:OPENEDGES is seeking highly motivated, qualified individuals to join the Design Verification (DV) team for our upcoming configurable cache coherent Network-on-Chip (NoC) program. This exciting position based in San Jose, CA, or Austin TX, offers opportunities to work within a veteran team of industry experts to solve state of the art DV challenges as they apply to the complexities of a coherent mesh fabric. Currently we are staffing the team for several levels and are interested in folks who are attracted to working in entrepreneurial environments with small to mid-size teams. We are looking for team players with alignment for these types of products with aggressive schedules, have hands-on experience in all aspects of DV efforts, and can bring to bear their expertise in making our effort a success.Roles & Responsibilities:The successful Design Verification Engineer (DVE) will be responsible for:Collaborating with architecture/design teams to understand the NoC designApply state of the art methods to author comprehensive DV plans/schedules/trackingEstablish and/or contribute to required DV flows/methodologiesWork with vendors to integrate UVM-based verification IP into a complete testbench solutionDetermine and implement required UVM-based correctness checkingCreating a UVM-based constrained random stimulus suite to achieve high coverageImplement UVM-based tracking methods to acquire and track coverage to closureHands-on debugging simulation fails down to root-cause (Verilog RTL)Demonstrating good communication skills, works well in small dynamic teamsRequired Qualifications:The ideal DVE candidate will have a reasonable mix of the following credentials:MSEE/MSCE +5 years, BSEE/BSCE +(5-10) years of relevant experience/track recordKnowledge/experience in the following areas: 1) Cache coherent memory architectures and NoC designs, 2) AMBA buses: CHI, CSL, AXI(n), ACE, APB, 3) Standard IP: DDR(x), PCI, PCIe, ARM, X86, RISC-VHands-on development of testbenches using Verilog, SV/UVM, RAL, SVA, ABV, UPF, XPropExperience in installing/configuring vendor IP for highly integrated testbench designExperience using industry standard toolsetsScripting languages: PERL/Python/Tcl/XMLPreferred Qualifications:Formal verification methods, emulation experienceBenefits:Medical, dental, and vision benefitsLife insurance401k retirement planPaid time off, paid holidays, sick leave, etc.
Job Title
Design Verification Engineer