Job Title

Position: Engineering Lead / Sr. Engineer (ASIC with UVM)Location: Markham, Ontario or Vancouver, British Columbia (Day-1 onsite)Hire Type: FulltimeJob Description The Candidate who has the passion to work on leading edge technology, who have solid verification capability and communication skills will be successful in this role.Strong team spiritDrive to completionFluent verbal English and good communicationKey Responsibilities:IOHUB (Immuno-Oncology hub) Subsystem test plan creation, DRVR implementation and verification closure.Closely work with Design/Architecture team to develop new verification components in the Testbench.Support SoC (system-on-chip) to complete IOHUB (Immuno-Oncology hub) IPs interoperability testing with external IPs at system level.Attend conference call for status sync up with global team.Preferred Experience:System Verilog & UVM (Universal Verification Methodology) is a must.IP verification or SoC (system-on-chip) verification is required either one or both is requiredGlobal company working experience background, fluent oral EnglishComplex IP/ASIC (Application-Specific Integrated Circuit) /SOC Design Verification, direct experience in IP/SOC or Processor (CPU or GPU) or Industry bus standard (PCI-e, HT) is preferred.Good knowledge of UVM/Verilog/System C/System Verilog.Solid background with hardware verification methodologies such as coverage-based verification methodology with the use of hardware assertions (PSL or SVA), insights into random techniques.Knowledge of Fabric and Virtualization is an asset.Scripting languages (Perl, C Shell, Makefile,) experience.Academic Credentials:Masters degree in electrical engineering within 3+ years, or bachelors degree in electrical engineering within 5+ years experience in digital ASIC (Application-Specific Integrated Circuit) / SOC (system-on-chip) design verification.