Job Title

ASIC DV Engineer Location: Remote- Canada The candidate would work closely with a team of designers, architects, and verification engineers to design and implement various display technologies. KEY RESPONSIBILITIES: Develop well designed and qualified display features Lead micro-architecture and design efforts based on high level architectural requirements Able to build complex systems to meet various design requirements including (but not limited to) functionality, performance, power, area, scalability and testability. Timely develop functional and implementation specifications, as well as test plans Develop and execute implementation and validation plans of the feature. Proactively driving and resolving any issues that may arise during the development stage Resolve pre-layout and post-layout timing and functional eco issues Mentor junior engineers to complete their tasks. PREFERRED EXPERIENCE: Minimum 7 years of ASIC design work experience Have in depth knowledge of entire design process from design specification, defining architecture, micro-architecture, RTL design and functional verification, synthesis, timing and formal verification Proficiency of Verilog or SystemVerilog Experience with multi-clock domain designs Experience in IP development Knowledge in video/display standards a plus. Strong in both written and verbal communication Strong analytical thinking and problem-solving skills Good teamwork and interpersonal skills ARM GLS Skill set. Good DV Skill with major GLS work experience. Expertise in testbench updates for GLS Expertise in Scripting languages perl or python Experience with Make, Yaml & Json file systems. Experience with 0 delay simulations and post layout simulations with SDF back annotations (Best/Typical/Worst Case analysis). Good understanding of RTL synthesis , Static Timing Analysis & LEC Flows. Experience with flow optimizations such as Grey/Black-boxing techniques Good at communicating requirements/issues with Implementation, PnR and Design teams. Working knowledge of Confluence documentation , version system GIT and Project execution with JIRA. Thanks & Regards Sameer Ahmad Raas Infotek Corporation. 262 Chapman Road, Suite 105A, Newark, DE -19702 Phone: (302) 565-0068 Ext: 143 E-Mail: sameer.ahmad@raasinfotek.com|Website: www.raasinfotek.com Linkedin: linkedin.com/in/sameer-ahmad-031a0b185