Job Title

Job Location : North York or Ottawa at 505 March Road, Suite 100, Kanata ON K2K 3A4Job DescriptionWe are seeking an experienced FPGA engineer to join our team and work on the development of Open RAN (ORAN) radio systems. The ideal candidate will have a strong background in FPGA design and implementation, as well as experience with ORAN technologies related to Radios.Key Responsibilities :In this role you will work on FPGA design and verification tasks including :Running the FPGA build flow and generate FPGA images for software teamManage FPGA release notes and release version trackingPerform FPGA image lab testing with embedded linux environmentCreate new IP designs in RTL for control and data processing of different productsCreate test bench and test cases for new IP designs to ensure functional correctnessCreate new test cases for existing IP designs to increase functional coverageCreate new test cases for new and existing IP design to help with lab debuggingParticipate source code review using web based code review toolsTrouble shoot FPGA related issues in a system test environmentEngage with FPGA vendors for FPGA related issuesParticipate in technical discussion in system level issuesKey Qualifications :3+ years of experience in FPGA design and implementationB.Sc or B.Eng in Electrical Engineering or Computer Engineering or related fieldsExcellent verbal communication skills in scrum meetings and technical discussions.Excellent writing skills in creating high-quality design and verification documents, lab test instructions & reports and process improvement documents.Excellent collaboration mindset to work with software teams, system integration & verification teams, and customer support teams across time-zones.Required Experience & Skill Sets :Experience in full FPGA compilation flow using Vivado / Quartus toolsExperience in Vivado IP Integrator / Quartus Platform Designer in FPGA system integrationExperience in Chipscope / SignalTap tools to implement hardware debug logicsExperience in Timing Analysis and FPGA resource optimization using Vivado / QuartusExperience in Python, Tcl, Bash for script writing and basic file parsingExperience in VHDL / Verilog / SystemVerilog to write RTL designsExperience in SystemVerilog / Cocotb for verificationExperience in Questasim to run module level and subsystem level simulationsExperience in Embedded Linux environment for lab testingExperience in AXI interface suites for communication between FPGA fabric and ProcessorsExperience in source code management tools such as GitExperience in developing SoC FPGAs with embedded ARM processorsPreferred Experience & Skill Sets :Experience in C / C++ development in embedded Linux environmentExperience in embedded Linux boot flow and bring up on Altera / AMD SoC FPGAsExperience in system RDL for RTL register generationExperience in FPGA developments of Digital Signal Processing modulesExperience in FPGA developments of ORAN / eCPRI / 3GPP NR protocol implementationsExperience in UVM based RTL verificationUnderstanding of digital signal processing theory and digital communication theoryUnderstanding of ORAN / eCPRI specification and 3GPP LTE / NR specification #J-18808-Ljbffr