Design Verification Engineer Location: Vancouver, Canada - Portland, OR, - Austin, Texas - Remote Compensation: JuniorIntermediate: $80K$150K SeniorStaff: $150K$250K Role Overview Join our global CPU development team to verify next-generation RISC-V processors. Youll collaborate with experienced architects and designers to develop and refine verification methodologies, debug complex designs, and deliver high-quality, high-performance CPUs. Responsibilities Develop, enhance, and maintain SystemVerilog/UVM test environments Perform functional verification, regression management, and bug analysis Analyze CPU architecture and memory subsystems to devise optimal verification strategies Track coverage, create verification reports, and resolve issues across design stages Contribute to testbench infrastructure and provide technical mentorship Document verification processes and results Qualifications BS/MS in Electrical/Computer Engineering or related field 10 years of experience Proficient in SystemVerilog and UVM Strong analytical, communication, and documentation skills Background with CPU micro architecture Experience with functional coverage-driven and constrained-random verification Working knowledge of Formal verification desired Scripting in Python, Perl, or Shell Experience with ground-up testbench development Strong teamwork, initiative, and attention to detail About Andes Technology As a founding Premier member of RISC-V International and a leader in commercial CPU IP, Andes Technology drives global RISC-V adoption. Our scalable portfoliofrom ultra-efficient 32-bit cores to high-performance 64-bit out-of-order processorspowers next-generation SoCs across AI, automotive, communications, consumer, and data center markets. With ISO 26262 ASIL-D certified processors, advanced vector and DSP capabilities, the Andes Custom Extension (ACE) framework, and a robust AI hardware/software stack, Andes enables optimized performance, power, and area efficiency. Over 16 billion Andes-powered SoCs are in production worldwide. Learn more at www.andestech.com . Start Your RISC-V Journey with Andes:
Job Title
RISC-V Design Verification Engineer (Mid-Staff)