Job Title

Join the leading chiplet startup! As an Eliyan Synthesis and STA lead, you will be working at a fast-paced early-stage startup creating technologies that fuel tomorrows chiplet based systems with best-in-class power, area, manufacturability, and design flexibility. You will be responsible for putting together synthesis and STA methodologies for best-in-class PHYs and Controllers. You will work with a cross-functional team of experts that operate from first principles, innovate and push the envelope to create high-volume and high-performance manufacturable products. We offer a fun work environment with excellent benefits. Key Responsibilities Responsible for creation of a highly flexible synthesis framework supporting multiple process technology nodes, block, chip specific customizations, wire-load, physical-aware synthesis and flexible choice of EDA tools Create dashboards for early architectural and implementation explorations for ease of comparison (PPA) Work closely with design and DFT teams to define a scalable, hierarchical constraints methodology that supports various mission, test modes & scenarios Work closely with physical implementation teams to define the optimal MMMC corners for various stages of implementation visvis placement, CTS and routing Responsible for putting together an STA signoff document per process node per foundry Responsible for STA signoff, generation of timing signoff ECOs that implementation teams can incorporate Responsible for debugging complex constraint issues or timing challenges during implementation Define an effective strategy to achieve high throughput of PNR and ECO cycles Champion the functional ECO implementation methodology Manage the LEC methodology, tool choice and mapping constraints required for block and chip level Manage the UPF/CPF flow for synthesis including timing methodologies with levelshift and isolation cells as necessary Qualifications Bachelors or Masters or Ph.D in Electrical Engineering and related fields, or equivalent 12+ years of experience in high-speed design synthesis and STA closure Handson experience with ASIC timing constraints generation, constraints validation (3rd party tools), and timing closure Expertise and advanced knowledge of industry standard timing tools (PT, Tempus) Strong understanding and experience in timing closure of various functional and test modes Expertise in deepsubmicron process and impact on timing visvis noise glitch, OCV, IRSTA, crosstalk Proficient in scripting (Tclk, Perl, Python) Proven track record of being a highly visible contributor as part of a startup like environment Problem solver and efficient in written/verbal communication excellent data organization skills and churns high quality work product Ability to work cross-functionally with digital and analog design, DFT, implementation teams #J-18808-Ljbffr