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Join to apply for the Custom Layout Engineer (1 yr contract) role at AMD This range is provided by AMD. Your actual pay will be based on your skills and experience talk with your recruiter to learn more. Base pay range $84,000.00/yr - $126,000.00/yr WHAT YOU DO AT AMD CHANGES EVERYTHING At AMD, our mission is to build great products that accelerate nextgeneration computing experiencesfrom AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinary. When you join AMD, youll discover the real differentiator is our culture. We push the limits of innovation to solve the worlds most important challengesstriving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the future of AI and beyond. Together, we advance your career. The Role Join a highimpact team building industryleading silicon for gaming consoles and nextgen compute. The hybrid scope covers fullcustom layout and I/O ring assembly/physical verification, with the emphasis shiftingand potentially predominatingon one side depending on schedule and integration demands, giving you endtoend exposure from transistorlevel design to toplevel signoff and tapeout. Youll collaborate closely with custom circuit designers, I/O and ESD experts, SoC integration, and CAD/flow teams while working on blocks like PLLs, DLLs, VCOs, highspeed differential interfaces, DACs, and robust I/O pad rings. Expect a fastpaced, collaborative environment with modern nodes, mature flows, and opportunities to influence methodology and mentor other junior engineers. The Person Thrives in dynamic environments and enjoys contextswitching between custom layout tasks and physical verification/integration work. Strong communicator who can translate design intent into clean, manufacturable layouts and drive closure on verification issues across teams. Detailoriented, qualityfocused, and comfortable owning deliverables through signoff and tapeout. Curious and proactive, eager to refine flows, automate repetitive tasks, and share best practices. Teamfirst mindset, with the initiative to lead design/ESD reviews and support teammates when needed. Key Responsibilities Custom Layout Create clean, robust layouts for digital and analog building blocks at the transistor level in Cadence Virtuoso. Floorplan, route, and assemble lowerlevel cells into macros and pads; integrate analog macros, power pads, and I/O pads. Build blackbox/abstract models and views consumed by other teams; contribute to tapeout collateral for custom blocks. Run hierarchical checks at cell/macro levels (DRC, LVS, ERC, EM/IR, Latchup/ESD) and iterate to closure in partnership with circuit owners. I/O Ring Verification Construct product I/O rings using established flows/scripts; generate and maintain views (Verilog, DEF, SPICE, GDSII). Perform physical verification on large designs (LVS, DRC, ERC, PERC), including visual inspections and incontext XOR. Track IP versions, facilitate ESD/LUP reviews for the ring and thirdparty IP, and deliver waivers/signoff documentation to SoC teams. Debug integration issues across macros/IPs/RDL within the I/O ring database and drive closure with crossfunctional partners. Preferred Experience Strong understanding of CMOS device/circuit theory and analog/digital layout best practices. Custom layout using Cadence Virtuoso; chiplevel integration concepts and ESD/LUP fundamentals. Physical verification using Mentor/Siemens Calibre (LVS, DRC, PERC) and ERC/EM/IR flows; familiarity with Synopsys ICC/ICC2/ICV is a plus. I/O ring assembly, RDL concepts, and generation of Verilog/DEF/SPICE/GDSII views. Debug skills for PV and integration issues; experience coordinating with IP and SoC teams. Scripting/automation in Perl, TCL, SVRF/TVF, SKILL; Python familiarity is a plus. Exposure to advanced nodes (e.g., 2nm/3nm; experience at 5nm/7nm also valued). Background with IP/standardcell layout, highspeed differential signaling, PLL/DLL/VCO, DACs, power pads, and incontext XOR. Academic Credentials Bachelors degree in Electrical or Computer Engineering preferred. Electronicsrelated diplomas with strong handson experience desired. LOCATION: Markham, Vancouver, Ottawa Benefits offered are described: AMD benefits at a glance. Seniority level MidSenior level Employment type Fulltime Industries Semiconductor Manufacturing Referrals increase your chances of interviewing at AMD by 2x Get notified about new Layout Engineer jobs in Markham, Ontario, Canada. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or feebased recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or thirdparty affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants needs under the respective laws throughout all stages of the recruitment and selection process. #J-18808-Ljbffr