Principal Engineer CAD Physical Verification Join to apply for the Principal Engineer CAD Physical Verification role at Microchip Technology Inc. Are you looking for a unique opportunity to be a part of something great? Want to join a 17,000-member team that works on the technology that powers the world around us? Looking for an atmosphere of trust, empowerment, respect, diversity, and communication? Microchip Technology Inc. offers all that and more. People appreciate our culture of growth, stability, and innovation, supported by our Vision, Mission, and Guiding Values. Job Description The CAD group at Microchip offers global support for multiple technology nodes and tools used in product development. The candidate will focus on flow development and support for backend physical verification. A solid software background and an interest in semiconductor chip design make this an ideal role. Expertise using Siemens Calibre and/or Cadence Pegasus DRC, LVS, and PERC tools is paramount. The candidate should run the tools, debug results, develop verification run decks, and automate flow and procedures. A strong understanding of both digital and analog design is essential, as development spans various design styles and requires knowledge of circuit, electrical, layout, and physical aspects. Responsibilities Develop physical verification regression test cases to QA physical verification decks Support Layout and Design engineers with physical verification activities using Siemens Calibre, Cadence Pegasus, or Synopsys Hercules Utilize advanced EDA methods to support ESD, ERC, VoltageAware DRC, viadoubling methodologies, etc. Collaborate with Technology Development and Device Engineering to develop DRC rules, additional devices, and designformanufacturability checks Develop rule decks as needed to support flow Verify and enhance foundry rule decks Support remote sites worldwide with layout verification activities Debug physical verification issues Work as a member of a team to develop flows that improve device quality and reliability The tasks a candidate will be assigned depend on their experience. Potential task assignments include building regression test cases for several PDKs, supporting PDKs from TSMC, Global Foundries, Vanguard, Dongbu, Magnachip, and more, and setting up Calibre/Pegasus PERC for several PDKs. Requirements 8+ years developing and supporting physical verification activities Indepth knowledge of Calibre DesignRev scripting Fluent with SVRF and TVF Accomplished at debugging PV issues with RVE, Vue, or other EDA visualizers Familiar with customizing Calibre Interactive; skilled with Tcl/Tk, Perl, Python, and other programming languages, inside and outside EDA tools Solid knowledge of layout rules and concepts, device identification concepts, and foundry rules Strong knowledge of Design for Manufacturing solutions affecting quality, reliability, and yield of designs Prefer extensive knowledge of Calibre/Pegasus/Hercules syntax and semantics, or similar layout verification tool Strong knowledge of Cadence Virtuoso and/or CalibreDRV Prefer Extraction, Reliability, and Dynamic Noise related knowledge Excellent verbal and written communication and interpersonal skills Travel Time 0% - 25% Pay Range We offer a total compensation package that ranks among the best in the industry. It consists of competitive base pay, restricted stock units, quarterly bonus payments, health benefits that begin day one, retirement savings plans, and a leading IESPP program. The annual base salary range for this position is $107,000 - $157,000.* Range is dependent on numerous factors including job location, skills, and experience. Ontario Accommodation Your accessibility is important to us. If you would like to contact us about our website or need help completing the application process, please email . In accordance with applicable laws (including human rights and accessibility legislation in Ontario), accommodation will be provided in all parts of the hiring process. Let us know what type of accommodations you require to help remove barriers so that you can participate throughout the interview process. This contact information is for accommodation requests only and cannot be used to inquire about the status of applications. Recruitment Agency Notice Microchip Technology Inc. does not accept unsolicited agency resumes. Please do not forward resumes to our recruiting team or other Microchip employees. Microchip is not responsible for any fees related to unsolicited resumes. #J-18808-Ljbffr
Job Title
Principal Engineer - CAD Physical Verification