Job Title

About the Role We are seeking a highly experienced and motivated Principal Analog Design Engineer to lead the design and validation of cutting-edge analog circuits for high-speed (112G and 224G) SerDes applications. In this role, you will be a key technical driver in the definition, execution, and validation of complex analog and mixed-signal designs. As a principal-level engineer, you will be expected to demonstrate a proven track record of delivering high-quality results in advanced FinFET CMOS technology within high-speed SerDes design environments. Responsibilities Actively participate in technical discussions across multiple disciplines, including analog/mixed-signal design, post-silicon validation, and system-level collaboration. Provide technical direction and mentorship to layout and less experienced analog design engineers, fostering a collaborative and knowledge-sharing culture. Engage closely with cross-functional teams, including systems, digital design, and test engineering, to ensure robust design implementation and validation. Strong problem-solving skills, analytical thinking, and a commitment to execution excellence are essential. Leverage excellent documentation and presentation skills to clearly communicate complex design concepts and results. Required Skills and Experience Experience in analog/mixed-signal circuit design for high-speed SerDes applications. Proven expertise in one or more of the following areas: PLL, CDR, CTLE, DFE, ADC, or Transmitter (TX) design. Strong understanding of high-speed communication standards such as PCIe (Gen5/Gen6) and Ethernet (100G/400G/800G). Solid foundational knowledge of analog design principlesnoise, jitter, matching, stability, and linearity. Hands-on experience with advanced FinFET CMOS process technologies (7nm or below). Proficiency in analog design and simulation tools such as Cadence Virtuoso/ADE, HSPICE, or equivalent. Experience in silicon bring-up, post-silicon validation, and lab debug of analog circuits. Excellent communication, documentation, and presentation skills. Strong problem-solving attitude and ability to deliver under tight schedules in a collaborative environment. Proven ability to mentor junior engineers, guide layout implementation, and drive design reviews. Demonstrated leadership in cross-functional technical discussions and decision-making. Team player with a collaborative mindset, willingness to share knowledge, and a hands-on approach to problem-solving. Preferred Skills and Experience Deep expertise in transmitter and receiver architecture, CDR loops, equalization techniques, and advanced ADC architectures. Familiarity with next-generation standards such as PCIe 6.0+, 800G/1.6T Ethernet, JESD, and other SerDes protocols. Hands-on experience in behavioral modeling (Verilog-A), MATLAB-based analysis, and automation scripting (Python/Tcl/Perl). Strong understanding of signal integrity, channel modeling, and system-level link performance. Qualifications Master''''s degree in Electrical Engineering, Electronics Engineering, or related field. PhD preferred. 8+ years of experience in analog design for high-speed SerDes (56G/112G/224G) applications. Job Type: Experienced Hire Shift: Shift 1 (Canada) Primary Location: Canada, Toronto Additional Locations: Work Model for this Role This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. Job posting details (such as work model, location or time type) are subject to change. Canada Accommodation: Intel is committed to a culture of accessibility. Intel provides accommodations to applicants and employees with disabilities. Find information and request accommodation here. * ADDITIONAL INFORMATION: Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. If you are asked to pay any fees during our hiring process, please report this immediately to your recruiter. #J-18808-Ljbffr