Job Title

Overview We are seeking a highly experienced Architect specializing in highspeed SerDes design with deep expertise in advanced analog/mixedsignal circuits, XSR (ExtraShortReach) interfaces, and optical I/O technologies. In this role, you will provide technical leadership across complex, nextgeneration PHY architectures, driving innovation from concept through production. You will work with crossfunctional teams and influence strategic direction across product lines while solving highly complex design challenges in advanced process nodes. Key Responsibilities Lead the architectural definition of the E224+ SerDes, including identifying required modifications to meet customerdriven performance, power, and latency targets. Architect and specify highperformance analog frontends, including CTLE/DFE, TX FIR filters, PLLs/CDRs, ADC/DACbased architectures, and clocking subsystems. Updated channel modeling assumptions VSRspecific equalization strategies AFE repartitioning and optimization Clocking improvements and tighter jitter budgets Lead feasibility analysis and modeling of nextgeneration SerDes channels, including electrical, XSR, and optical interconnect environments. Drive innovation in optical I/O, including modulator/driver integration, TIAs, and photonicselectrical codesign workflows. Technical problemsolving leading debug of complex silicon issues spanning analog, digital, packaging, and optical domains. Develop innovative solutions to challenging PHYlevel problems using deep expertise in circuits, channel modeling, and system behavior. Partner with crossdisciplinary teams to contribute to longterm technology strategy in SerDes, chiplets, and opticalinterconnect domains that are aligned to industry trends. Analog & MixedSignal Design Define and guide development of critical analog building blocks: CTLE, DFE, slicers Highspeed TX drivers and VSRtuned FIR tap structures CDR/PLL architectures supporting subps jitter ADC/DACbased receive architectures, if applicable Optimize AFE and receiver signal chains for VSR channels, extremely low reach, and tighter insertionloss budgets. Guide design teams through detailed analog/mixedsignal design, circuit partitioning, performance optimization, and silicon validation strategy. Review and approve blocklevel and toplevel designs, ensuring alignment to architectural intent and performance targets. Collaborate with layout, modeling, signalintegrity, packaging, and system teams to optimize endtoend performance and power. Required Qualifications 15+ years of experience in analog/mixedsignal circuit design, SerDes PHYs, or related highspeed I/O. Proven track record architecting multigeneration SerDes PHYs, preferably at 56G+, 112G+, or 224G+. Deep expertise in analog building blocks: LNAs, TIAs, CTLE, DFE, TX drivers, PLL/CDR, ADC/DACbased SerDes. Handson silicon bringup experience in SerDes or highspeed analog designs. Experience working with foundries on advanced process nodes (e.g., 5nm, 3nm). Skilled in simulation/verification (Spice, AMS), modeling (Matlab/Simulink, VerilogA), and lab measurement methodologies. Handson knowledge of XSR/USR interfaces and chipletbased architectures. Demonstrated ability to lead large, crossfunctional technical initiatives with minimal oversight. Preferred Qualifications Experience with DSP equalization, MLSD, or nonlinear cancellation for 224G+ operation. Experience with optical links, copackaged optics, optical modulators, drivers, and photonics integration a strong asset. Strong understanding of signal integrity, channel modeling, equalization techniques, and advanced packaging (2.5D/3D, interposers). Publications, patents, or industry recognition in highspeed I/O or optical domains. Ability to mentor senior designers and uplift organizational technical capability. #J-18808-Ljbffr