Job Title

We Are: At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from selfdriving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of highperformance silicon chips and software content. Join us to transform the future through continuous technological innovation. You Are: You are a seasoned engineer with deep expertise in highspeed serial communication and transceiver design, blending theoretical rigor with handson laboratory proficiency. You thrive in dynamic, crossdisciplinary environments, collaborating with analog, digital, and hardware teams to realize innovative solutions. Your background includes advanced modeling, signal processing, and hardware validation, making you a pivotal contributor to projects involving PCIe and Ethernet protocols. You have a natural inclination for mentoring, guiding junior engineers, and sharing your technical wisdom. Your analytical mindset and attention to detail help you anticipate challenges and craft robust architectures. As an adaptable problem solver, you excel at troubleshooting complex systems and supporting customers through technical challenges. You are passionate about advancing connectivity technologies and are eager to lead simulation and signoff activities that ensure bestinclass product reliability. With your strong communication skills, you foster transparency and alignment across teams, and your commitment to excellence drives Synopsys continued leadership in highperformance connectivity solutions. You are motivated by opportunities to innovate, empower others, and make a tangible impact on nextgeneration silicon products. What Youll Be Doing: Collaborating closely with analog, digital, and hardware teams to ensure holistic design and verification coverage. Developing and maintaining comprehensive simulation and verification plans for IP, aligning with reliability and performance targets. Reviewing execution against verification plans through regular meetings with multiple verification teams (analog, cosim, DV, GLS, formal, emulation). Establishing, monitoring, and reporting on key verification metrics such as functional, code, and assertion coverage. Coordinating with Firmware & Algorithms Lead and Digital FW Developers to develop hardware regression plans for successive FW releases. Delivering highquality verification collateral including test plans, test cases, coverage reports, and signoff documentation. What Youll Need: MSc or PhD in Electrical/Computer Engineering, with 10+ years of relevant industry experience. Deep expertise in highspeed protocolsPCIe and Ethernet. Proficiency in SystemVerilog, objectoriented verification, UVM/VMM/OVM, and assertionbased verification, coverage closure expertise. Strong scripting/programming: Python, TCL, Perl, C/C++. Indepth knowledge of highspeed analog and digital design principles. Familiarity with verification flows: analog, cosimulation, digital verification, GLS, formal methods, and emulation. Proven leadership: testbench architecture, planning, crosssite collaboration, and mentoring. Who You Are: Innovative and forwardthinking, always seeking new solutions to technical challenges. Detailoriented, with a rigorous approach to analysis and validation. Collaborative and effective in crossfunctional team settings. Strong communicator and mentor, able to share knowledge and guide others. Adaptable, thriving in fastpaced and evolving environments. Customerfocused, dedicated to delivering highquality support and solutions. The Impact You Will Have: Advance highspeed connectivity for enterprise and hyperscale applications worldwide. Ensure robust and scalable solutions for a diverse global customer base. Drive innovation in SerDes design, modeling, and validation methodologies. Accelerate timetomarket for cuttingedge silicon products. Empower customers by delivering expert technical support and troubleshooting. Strengthen Synopsys reputation as an industry leader in highperformance connectivity IP. Enable successful silicon implementation by catching issues early through rigorous simulation and verification. Facilitate crossteam collaboration that enhances product quality and reliability. The Team Youll Be a Part Of: Youll join a worldclass engineering team focused on developing, verifying, and delivering industryleading highspeed connectivity IP. Our team is a blend of domain experts in analog and digital design, modeling, and hardware validation, working collaboratively to push boundaries in SerDes and transceiver technologies. Together, we drive innovation, tackle complex challenges, and ensure our products empower customers to achieve their goals in enterprise, data center, and networking applications. #J-18808-Ljbffr