They gather information about your interactions on the site, such as which pages you visit frequently, how long you stay, and the links or buttons you click. They help us record any difficulties you have with the website and help us to evaluate the effectiveness of our advertising. By analyzing this data, we can understand what aspects of our site are effective and identify areas for improvement.* This is a secondary processing purpose.* This is a secondary processing purpose.* This is a primary processing purpose.* This is a secondary processing purpose.Cienas next-generation Wavelogic Digital Signal Processor (DSP) programs rely on deep technical excellence, cross-functional collaboration, and continuous innovation. This role offers the opportunity to shape the frontend implementation of industryleading ASIC technology and contribute to the methodologies that keep Ciena at the forefront of highperformance optical networking.B.Sc. in Electrical Engineering, Computer Engineering, or a related discipline (or equivalent experience) Industry experience using synthesis and/or static timing analysis tools within an ASIC development environment Knowledge of ASIC implementation flows, including synthesis, timing analysis, logical equivalence checking, and clock domain crossing validation Familiarity with RTL design principles and hardware description languages Ability to work effectively within multidisciplinary engineering teams and manage deliverables to project schedulesExperience with additional frontend or backend design activities such as floorplanning, Design for Testability (DFT), or place and routeScripting experience (e.g., Python, Tcl, or similar) to enhance automation and debug workflowsExperience working with external EDA vendors or foundry technology teams Pay ranges at Ciena are designed to accommodate variations in knowledge, skills, experience, market conditions, and locations, reflecting our diverse products, industries, and lines of business. Please note that the pay range information provided in this posting pertains specifically to the primary location, which is the top location listed in case multiple locations are available.Non-Sales employees may be eligible for a discretionary incentive bonus, while Sales employees may be eligible for a sales commission. In addition to competitive compensation, Ciena offers a comprehensive benefits package, including medical, dental, and vision plans, participation in 401(K) (USA) & DCPP (Canada) with company matching, Employee Stock Purchase Program (ESPP), Employee Assistance Program (EAP), company-paid holidays, paid sick leave, and vacation time. We also comply with all applicable laws regarding Paid Family Leave and other leaves of absence. #J-18808-Ljbffr
Job Title
Senior ASIC Synthesis and STA Engineer