Job Title

At AMD, our mission is to build great products that accelerate nextgeneration computing experiencesfrom AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinary. When you join AMD, youll discover the real differentiator is our culture. We push the limits of innovation to solve the worlds most important challengesstriving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the future of AI and beyond. The Role The I/O Pad Ring Team is looking for a candidate to perform I/O pad ring physical verification duties and methodology improvements on multiple exciting AMD products being created today. I/O Pad Ring refers to the input/output interfaces that are loosely found in a ring around the chip. Interfaces such as PLL (phase lock loop), DDR, GDDR, USB, HDMI, PCIE, and GPIO all reside in the IO Pad Ring. SOC level verification takes many days; the IO Pad Ring function takes a subset of analog IPs to preverify them in order to prefetch any issues prior to final integration. This team is essential to the success of AMD as a cuttingedge company. You will be working on some of the most exciting projects the industry has to offer, such as CPU/GPU/APU and semicustom products featured in Sony PlayStation and Microsoft Xbox. The Person The candidate will excel in problemsolving/debug skills and be able to see through the latter stages of a product delivery. Strong communication skills will also be required. Key Responsibilities Daytoday responsibilities include assembling macros/IPs/RDL into an I/O pad ring database and running various verification tools on that assembled database to determine integration issues. If issues are discovered, communication with various IP owners may be required to facilitate issue resolution. Verification tasks include Design Rule Check, Layout VS Schematics, Electronic Rule Check, and Latchup/Electrical Static Discharge. Construction of product I/O pad rings using established flows and scripts. Generated views include Verilog, Def, Spice, and GDSII. Physical verification on designs that contain up to 200M devices including: LVS, DRC, ERC, and PERC. Delivery of all needed waivers (Electronic Rule Check / Design Rule Check / EDRC / PERC) and documentation to SoC teams. Facilitate ESD and design reviews for 3rd party IPs and I/O ring. Tracking of IP versions, visual inspections, and incontext XOR verifications. Preferred Experience Strong understanding of physical verification checks (Layout VS Schematic, Design Rule Check, Electronic Rule Check, PERC) and ability to debug and resolve issues. Knowledge of chiplevel integration and Electrical Static Discharge / LUP concepts. Ability to communicate with various teams to articulate issues and requirements related to layout to facilitate solutions. Physical verification experience using Mentor Calibre (Layout VS Schematic, Design Rule Check, PERC) and Synopsys tools (ICC/ICC2/ICV). Experience doing physical verification for a tile of chip physical design would be an asset. Perl programming, TCL, SVRF, TVF programming not required, but would be advantages. IP layout design experience and exposure to Cadence is a plus. Must be able to work independently and as part of a team. Academic Credentials Electrical, Computer, Biomedical, or Mechanical Engineering degree and/or Electronicsrelated diploma. Benefits offered are described: AMD benefits at a glance. AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMDs ''Responsible AI Policy'' is available here. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or feebased recruitment services. AMD and its subsidiaries are equalopportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or thirdparty affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants needs under the respective laws throughout all stages of the recruitment and selection process. This posting is for an existing vacancy. #J-18808-Ljbffr