WHAT YOU DO AT AMD CHANGES EVERYTHING At AMD, our mission is to build great products that accelerate nextgeneration computing experiencesfrom AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinary. When you join AMD, youll discover the real differentiator is our culture. We push the limits of innovation to solve the worlds most important challengesstriving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the future of AI and beyond. Together, we advance your career. THE ROLE: As a Physical Implementation Architect, you will lead all aspects of RTL development, physical implementation during IP development to closure at SoC level, from RTL optimization through all stages of Physical Design closure. You will set technical direction, mentor engineering teams, and ensure bestinclass power, performance, and area (PPA) for highspeed (>2GHz) designs with complex I/O clocking. THE PERSON: As a Physical Implementation Architect, you will collaborate with IP architects, RTL designers, physical design engineers, and NBIO IP team managers. You will drive physical implementation of IP through the entire physical design flow to achieve best PPA, while shortening the overall development schedule. This role provides an excellent opportunity for robust individuals looking to make a difference. This is an exciting time to join the AMD team. KEY RESPONSIBILITIES: Lead RTL optimization for physical implementation working with RTL team, starting from Architecture to final Physical Design closure, finding appropriate tradeoff for Power, Performance, Area (PPA). Drive methodology and execution of the overall teams execution through all stages of implementation synthesis, floor planning, placement, clock tree synthesis, routing, fullchip timing, closure for advanced SoC projects. Architect and implement reference methodologies and automation scripts for global SoC development. Provide technical leadership for multiple I/O protocols, chiplet interfaces, including PCIe, UCIe, UAlink, Ethernet, and Infinity Fabric linklayer. PREFERRED EXPERIENCE: Mastery of RTL optimizations to facilitate PD closures Deep understanding of CDC, RDC, LINT, STA constraints development Logical equivalence checking using industry standard tools Closure of lastmile timing, including functional ECO, and timing closure Automation using TCL and Python, including use of AI for Design 15+ years of industry experience in physical implementation leadership. Synthesis, Floorplanning, Placement, clock trees synthesis, PostRoute Timing closure for highspeed >=2GHz designs. Deep expertise in physical design methodologies for highspeed (>2GHz) SoCs This role is not eligible for visa sponsorship. ACADEMIC CREDENTIALS: MS, or PhD in Electrical or Computer Engineering LOCATION: Markham, Ontario; Vancouver, Canada; Austin, TX Benefits offered are described: AMD benefits at a glance. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or feebased recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or thirdparty affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants needs under the respective laws throughout all stages of the recruitment and selection process. AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMDs Responsible AI Policy is available here. This posting is for an existing vacancy. #J-18808-Ljbffr
Job Title
Physical Implementation Architect