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About Us:Tessolve is one of the largest global pureplay Digital ER&D silicon design services companies offering end-to-end turnkey new product design offerings with a unique combination of pre-silicon and post-silicon DNA to provide an efficient turnkey solution from silicon bring-up, and spec to the product design lifecycle. With a global engineering team of over 3200+ employees and a presence across 12 locations worldwide, Tessolve is a comprehensive one-stop product engineering services & technology solution provider. Our full services offerings span advanced silicon, hardware design, and embedded software capabilities, setting up Global Engineering Centres (GEC) bolstered by state-of-the-art infrastructure investments in silicon and system testing labs.Tessolve serves a diverse global clientele, including 9 of the top 10 semiconductor companies, OEMs & Tier 1 clients across multiple sectors, start-ups, and government & defense entities. Our global footprint includes offices in the United States, India, Singapore, Malaysia, Germany, United Kingdom, Canada, Netherlands, Japan, Taiwan, Thailand and the Philippines, with global delivery & testing labs strategically located in India, USA, Singapore, Germany and Malaysia. Visit us at learn more.Job OverviewThe Synthesis and STA Lead Engineer will be responsible for overseeing the synthesis process and ensuring the accurate timing analysis of designs. This role requires a deep understanding of VLSI design principles and extensive experience with synthesis tools and static timing analysis (STA).The ideal candidate should have a strong background in digital design, experience with EDA tools, and a thorough understanding of the synthesis and timing closure process.Key Responsibilities- Leading the synthesis and STA activities for complex digital designs.- Developing and maintaining synthesis scripts and methodologies to improve efficiency and quality.- Collaborating with design and verification teams to ensure the successful integration of our designs & Synthesis and providing quality NL to RTL, DV & PD teams.- Setup LEC flow to run LEC between RTL-NL, NL-NL and run and provide LEC collaterals to other teams.- Analysing and resolving timing issues and ensuring that our designs meet all performance and power requirements.- Providing technical guidance and mentorship to junior engineers.