Job Title

As a Senior Memory Circuit Design Verification Engineer / Staff Memory Circuit Design Verification Engineer, you will work in a highly innovative, motivated, young and dynamic design team capable of verifying complete products using state of the art memory technologies. You will need to have the ability to drive the team and the overall verification effort to ensure the timely delivery of a functionally correct design.Hiring RequirementsResponsibilitiesWork on Custom Digital Design with a focus on timing-accurate, Netlist level verification.Own the end-to-end verification of critical features, from planning to closure.Guide and set the direction for the verification effort within your areas of expertise in any project that the team undertakes.Work closely with designers to root-cause logic issues, suggest fixes, and verify design updates.Collaborate with the Design, DFT, Layout, and PE teams to drive debug and improve design quality.Participate in developing verification methodology and verification environments for advanced DRAM and emerging memory products. Contribute to team knowledge through reviews and mentoring newer engineers.Unique OpportunitiesComplete ownership of verification and end-to-end analysis of complex full-chip gate-level custom designs with advanced low power and power management technologies spread across multiple categories such as HBM, DDR4, LPDDR4, DDR5, and LPDDR5 that are capable of operating at high speeds of up to 6400MT/s.Collaborate closely with design and verification team members spread across the globe, many of whom have decades of experience in memory design.Work on cross-functional tasks that can widen your skill set.Be part of a team where technical depth, initiative, and ownership are valued and nurtured.Skills and Experience Required:Bachelor’s or Master’s degree in Electrical/Electronics Engineering or related field.3-6 years of experience in digital design verification, preferably in a custom design environment.Strong grasp of timing-aware verification and schematic/netlist-level analysis.Experience with DFT and signal tracing in hierarchical designs.Solid scripting skills (Python, Perl) for automation and debugging support.Familiarity with tools like Virtuoso and waveform viewers.Strong problem-solving skills, attention to detail, and a passion for technical excellence.Excellent communication and teamwork skills.