Experience-8+ yearsInnovus expertise in designing Floorplan for SoCMust have a knowledge and implementation strategies to create an IO ring in accordance design specificationHave a deep knowledge on ESD, latch-up etc for foundry requirements and placement strategiesShould have a hierarchical design implementation knowledge which include partitions/HMs/tiles push down to each core/tileShould have a knowledge on feed through planning and implementation.PG creation and push down methodology's knowledge and implementationShould have a knowledge on Analog components and their requirements in placements according to design specificationsRDL knowledge and working with packaging is a must for SoC floorplan designerPV clean-up on floorplan and self-derive in all the sign-off including Physical Verification, ESD and foundry/Analog requirements anyDeep scripting knowledge is essentialSoft skills working with Packaging, design team and HM owners is essential
Job Title
SOC/ Fullchip Floorplan Lead