Experience: 10 - 15 Location-Hyderabad, Work from OfficeJob Description Key requirements Primary skill requirements of all engineers will be • Exceptional Digital fundamentals • Hands on experience in System Design with FPGA devices with relevant FPGA EDA tools • Experience in designing and implementing FPGA based solution in Microchip or Xilinx or Altera FPGAs • Write high quality code in Verilog/System Verilog, VHDL and C code for embedded processors. Maintain existing code. • Developing testbenches using Verilog/System Verilog and verifying validation designs in simulation environment using BFM/VIP • Experience in using Synthesis, Placement constraints • STA constraint definition and Timing closure for high speed designs • Validation of FPGA based implementation on HW board • Experience in writing embedded FW programs in C/C++ • Strong Lab debug experience and enthusiasm & patience to solve systems level hardware issues using Lab equipment, Embedded debuggers and RTL debuggers • Be conversant with on-chip debug tools • Experienced with scripting tcl/perl • Exposure to Version management systems, GitHub, SVN • Excellent verbal and written communication skills in English • Strong technical background in silicon validation, failure analysis and debug • Understand hardware architectures, use models and system level design implementations required to utilize the silicon features. Additional skills required are • Basic knowledge of embedded processors such as ARM Cortex-M3 or RISC-V and familiarity with AMBA protocols APB, AHB, AXI, ACE • Knowledge on embedded software C/C++ programming and bare metal application development and debug using Eclipse Theia IDE or equivalent • Board level debug skills using oscilloscopes, digital analyzers, protocol exercisers and analyzers, integrated logic analyzers (e.g. Synopsys Identify, Xilinx Chipscope) Skill needs based on experience Lead Engineer [Serdes/DDR/SOC/Configuration Security] o Strong hands-on FPGA Silicon validation experience o Must have protocol expertise in one or more of PCIe-Gen4/5, DDR-4/5, Ethernet, Processor based subsystem. o Knowledge of RISC-V processor is a plus o Proven track record of planning, executing and handling complex FPGA System Project using Processor based test cases o Be responsible for self and team level deliverables of assigned Use Model and Use Cases. Manage work assignments for a group of junior and senior engineers. o Train and mentor junior team members and bring them upto speed on the validation activity o Track and follow up on dependencies for design creation, embedded software drivers, IP, HW etc. o Support and provide guidance to junior team members in debugging issues o [Serdes] Excellent knowledge of PMA/PCS architecture, DFE, CTLE. Experience with compliance testing, interop testing and usage of Ethernet traffic testers, PCIe exerciser, network traffic testers etc. o [DDR] Excellent knowledge of the DDR memory interface training, initialization and controller validation. Use of debug equipment such as logic analyzers. Performance and stress testing of the interface for robustness. o [SOC] Excellent knowledge of processor subsystem validation, bus architecture, application development, NOC, vector processor, peripheral interfaces, boot modes, trace debug. Performance and bandwidth testing. o [Configuration & Security] Excellent knowledge of Embedded System development and debug on RISC-V/ARM, PQC, PUF, Crypto, Firmware, SI Characterization, Good at Mathematical Analysis, Expert in SPI/QSPI/Octal SPI, Exposure to Microchip FPGAs & flow o [Characterization] [DDR Char] Expertise in electrical characterization (PVT) and/or compliance of memory interfaces (DDR5/4/etc., LPDDR5/4/etc.) [Serdes Char] Expertise in electrical characterization (PVT) and/or compliance of serial interfaces such as PCIe, JESD204C, Ethernet, HDMI, USB4, etc. Experience in characterization of SoC, processors, PLL, Oscillators, etc. Experience with FPGA design flow (using Libero, Quartus, Vivado, etc.) using Verilog or VHDL Firmware Development on multi-core microcontrollers or processors (ARM/RISC-V or similar) Experience working in a laboratory environment, using lab equipment such as BERTs, logic analyzers, spectrum analyzers, oscilloscopes, function generators, etc. In-depth knowledge of electrical engineering fundamentals including CMOS device operation and characteristics Exposure to automated characterization flows to maximize use of equipmentThanks & Regards Kalpana Bhatia Team Lead-Talent Acquisition _______________________________________________________________________________ Mirafra Software Technologies Pvt. Ltd. Email: kalpanabhatia@
Job Title
FPGA Lead