We are looking for a talented and motivated ASIC/SoC Design Engineer to join our team and play a key role in the development of next-generation integrated circuits (ICs). This position offers the opportunity to work on a variety of tasks within the design flow, including logic synthesis, Formal Equivalence Verification (FEV), and Clock Tree Synthesis (CTS)/Clock Layout Planning (CLP).Responsibilities:Synthesis:Write synthesizable RTL code using Hardware Description Languages (HDLs) like Verilog or VHDLPerform logic synthesis using Electronic Design Automation (EDA) tools to optimize gate-level netlist for performance and areaAnalyze and debug synthesis reports to identify potential issuesFormal Equivalence Verification (FEV):Utilize formal verification tools to ensure the functional equivalence of pre- and post-synthesis designsWrite formal constraints and analyze verification results to identify potential design bugsClock Tree Synthesis (CTS) / Clock Layout Planning (CLP):Design and implement clock trees to meet timing constraints and minimize skewPerform clock tree analysis using EDA tools to ensure signal integrityGeneral Design Tasks:Participate in code reviews and ensure adherence to coding standardsPerform static timing analysis (STA) to analyze timing performanceCollaborate with design verification and physical design engineers throughout the design flowStay up-to-date with the latest advancements in design tools and methodologiesQualifications:Bachelor's degree in Electrical Engineering, Computer Engineering, or a related field (Master's degree a plus)5-7 years of experience in ASIC or SoC design with a strong foundation in RTL design and synthesisWorking knowledge of Formal Verification methodologies and tools is a plusExperience with Clock Tree Synthesis (CTS) and Clock Layout Planning (CLP) tools is a plusProficiency in Verilog or VHDL with a good understanding of digital design concepts (combinational logic, sequential logic)Experience with Electronic Design Automation (EDA) tools (synthesis tools, formal verification tools, STA tools)Strong analytical and problem-solving skillsExcellent communication and collaboration skills to work effectively in a team environment
Job Title
ASIC/SoC Design Engineer (Synthesis/FEV/CLP)