Job Title

Who we are:At UST, we help the world’s best organizations grow and succeed through transformation. Bringing together the right talent, tools, and ideas, we work with our client to co-create lasting change. Together, with over 30,000 employees in 25 countries, we build for boundless impact—touching billions of lives in the process. Visit us at We are looking for a candidate with knowledge and experience in Palladium and Zebu platforms for Emulation based functional verification tasks.Experience: 3+ years Working location: Remote (Work from home)Working time: 2pm-10pm ISTEducation: Bachelor’s or Master’s degree in computer engineering/Electrical Engineering Responsibilities:Develop test plans and test content for emulation-based functional verificationWork on Verilog code, emulation model compilation, and waveform debugsUtilize scripting languages such as Python and TCL for verification tasksHave a basic understanding of AXI and knowledge in PCIE would be a plusFamiliarity with System Verilog for verification tasksRequirements:3+ years' experience in Emulation domain.⁠Knowledge of Palladium and Zebu emulators.⁠Experience in emulation based functional verification which includes test plan definition and test content development.Have good understanding of Verilog, emulation model compilation, waveform debugs.Hands on experience in scripting languages like Python, TOLBasic understanding in AXI. Knowledge in PCIE is a plus.Basic understanding of System Verilog.Contact Ms. Anna - WhatsApp: +84 935059669Email: anh.thivannguyen@