Job Title

Location: Hyderabad, On-site - WFO Experience: 5-7 Years Mode of Interview: Virtual & F2F Preferred Candidate: Local Candidates & Immediate Joiners Shift Timing: General Shift Transport is Provided Key Skills: Primary Skills: 5+ Years of experience in SV, UVM, Test Bench Development, Soc, Full-chip verification, any memory experience Good to Have: GLS, STA, Python knowledge, circuit characterization Job Description & Responsibilities: Design verification role, with experience in Verilog simulation, UVM methodology, and full-chip verification, with memory experience being beneficial and preferred Candidate should have a quick learning ability, a positive attitude, and strong technical skills in system Verilog and UVM. Project involves Graphics DDR7, an industry-leading product. UVM simulation and full-chip verification are key skills, with a minimum educational requirement for a bachelor's degree. Familiarity with static timing analysis, GLS Familiarity with circuit characterization, timing libraries - files and formats, timing arcs. Familiarity with Python automation for test bench development is desirable Educational Qualification & Other skills: Strong communication skills, with the ability to convey complex technical concepts to other design peers in verbal and written form. A proactive learner with strong analytical and problem-solving skills."