Job Title: Lead Physical Verification Engineer Experience: 7+ Years Location: Bangloare/Hyderabad Employment Type: Full-time Industry: Semiconductors / ASIC / SoC / Foundry / VLSI Job Summary: We are seeking an experienced and detail-oriented Lead Physical Verification Engineer to drive and manage DRC/LVS/ERC/Antenna signoff for complex block and full-chip designs at advanced technology nodes. The ideal candidate will lead PV planning, execution, closure, and tool flow automation in collaboration with cross-functional teams and foundries. Key Responsibilities: Own and lead full-chip and block-level physical verification signoff (DRC, LVS, ERC, Antenna, Density). Collaborate with layout, circuit design, and physical design teams to resolve violations and ensure clean tapeouts. Interpret and implement foundry physical verification rule decks (TSMC, Samsung, Intel, etc.). Define PV methodologies and drive automation and flow optimization. Conduct floorplan-aware and hierarchical PV runs for large SoCs or custom designs. Review and resolve complex PV violations in hierarchical and flat designs. Coordinate with foundry/EDA vendors on rule deck updates and tool issues. Drive signoff timelines and tapeout readiness in coordination with program managers. Mentor and guide a team of PV engineers, perform technical reviews, and ensure best practices are followed. Required Skills and Experience: B.E/B.Tech or M.E/M.Tech in Electronics, Electrical, or VLSI Engineering. 7+ years of experience in Physical Verification for ASIC or custom layout designs. Deep expertise in PV tools such as: Calibre (Mentor/Siemens) for DRC/LVS/ERC/Antenna Cadence Assura/PVS , IC Validator (Synopsys) – a plus Proven track record of handling multiple successful tapeouts at advanced nodes (e.g., 7nm, 5nm, 3nm). Excellent understanding of layout principles, hierarchical flows, IP integration, and PDK handling. Strong scripting skills (Tcl, Python, Perl) for PV automation and data analysis. Strong leadership, problem-solving, and communication skills. Preferred Qualifications: Experience in analog-mixed signal or IO layout verification. Familiarity with EM/IR/DFM/DFY verification is a plus. Experience working across multiple foundry rule decks and EDA environments. Prior experience in mentoring or managing small to mid-sized PV teams. Interested can share Cv to
Job Title
Lead Physical Verification Engineer