Number of positions: 10 •2-6 Experience with micro architecture design and system design. Using Verilog, SV or VHDL. • Experience in Spyglass Lint, CDC, SoC Integration • Experience in Logic design with Verilog, SV • Experience in ASIC Synthesis, STA and timing closure • Experience in any Processor based system, design with SoC, AXI/AHB/APB System bus and peripherals Ethernet, PCIe, DDR , USB, UART, SPI , I2C etc • Synthesis, Timing Analysis through various industry standard tools. • TCL, Python Scripting Notice Period: Immediate to 1 Month BLR/Hyd locations
Job Title
ASIC RTL Designers Lint/CDC