JOB DESCRIPTION :- IP verification Using SV/UVM or SOC Verification using C/SV VIP Integration Interconnect Protocols: .DDR/PCIe/Mipi/USB/Image Sensing/Ethernet/CXL/Dispalyport/UCI/ Power mgmt. SOC Interfaces: GPIO, SPI, I2C, UART (3+) High Speed Serial Interfaces: PCIe Gen 3/4 or USB or MIPI or UPF or DDR Coverage Closure: Code, Functional and Toggle Tools: Synopsys VCS or Cadence Incisive Technical Documentation: Testbench Specification, Test Plan Specification Good exposure to Scripting skills like Perl or Python or Shell or TCL Bachelors in Electronics Engineering is a minimum requirement Masters in Electronics or Computer Science Engineering is an added advantage 5 to 15 years minimum Exposure to working in multi-national environment is required Excellent oral and written communication skills is a must. An attitude to learn and grow. Adaptability and flexibility are desired. GLS DV(5+yrs) Gate-Level Simulation Engineer with a strong background in RTL integration and gate-level validation. The role requires working closely with design and verification teams to ensure timing closure, power accuracy, and system stability. Hands-on IP verification experience is a valuable asset.
Job Title
Design Verification Engineer