Job Title

Roles & Responsibilities: Experience: 5 to 6 yrs Develop and implement FPGA logic using VHDL/Verilog and Vivado Block Designs . Work with Vivado 2017.2 or later , ensuring proper tool flow, constraint handling, and design timing closure. Develop and integrate 32-bit soft-core processors such as MicroBlaze and PicoBlaze into FPGA designs. Perform Clock Domain Crossing (CDC) analysis and apply best practices to ensure robust design. Write and manage XDC constraints to meet timing and functional requirements. Use on-chip debugging tools such as ILA , TSM (Trigger State Machine) , and logic analyzers for real-time debugging. Run simulations using tools like ModelSim , QuestaSim , or Vivado ISIM to validate functionality. Debug complex logic and system-level issues using a structured and analytical approach. Collaborate with hardware teams; exposure to schematic reviews and board-level debugging is a plus. Interpret high-level system or FPGA requirements and translate them into efficient logic architectures. Required Skills & Experience: Proven hands-on experience with Xilinx Vivado 2017.2 or later . Proficiency in VHDL , Verilog , and Vivado IP Integrator (Block Design). Deep understanding of MicroBlaze and PicoBlaze architectures and implementation. Expertise in timing analysis , CDC handling , and timing constraint writing . Hands-on experience using ILA , VIO , and debugging with state machines (TSM) . Familiarity with simulation tools such as ModelSim , QuestaSim , or Vivado ISIM . Strong analytical and logical debugging skills. Experience with hardware-level debugging and schematic understanding is a plus. Ability to write or interpret system-level and FPGA-specific requirements for design implementation. Preferred Qualifications: Bachelor’s or Master’s degree in Electronics , Electrical Engineering , Computer Engineering , or a related field. Experience working in domains such as telecom , embedded systems , defense , or industrial automation is an advantage. Familiarity with scripting languages like Tcl or Python is a plus.