Job Title

HCLTech is looking for a Senior Design Verification Engineer with strong experience in high-speed interfaces such as DDR,UCIe, PCIe, CXL, Ethernet, and NVMe. Location: Bangalore, Chennai, Hyderabad Experience: 5–14 years Interested? Send your resume to: Responsibilities: Develop test plans and verification infrastructure for complex IPs, subsystems, and SoCs. Build UVM-based verification environments. Create reusable BFMs, monitors, checkers, and scoreboards. Drive functional coverage and verification closure. Collaborate with architects, designers, and DFT teams. Skill Set: BTech/MTech with 4– 7years of relevant experience. Strong in System Verilog and UVM. Experience in IP/Sub-system/SoC level verification. Familiar with code coverage, functional coverage, and assertions. Hands-on with: UCIe or PCIe Bus protocols: AXI, AHB, APB Industry-standard simulation and debug tools Excellent debugging and communication skills. Plz refer in your connections and Groups for better reach