Tips: UVM, Design Verification. Responsibilities Develop UVM interface agents from scratch and integrate them into the testbench. Develop sequences, testcases, functional coverage as per testplan. Develop testplan by reading the specification in detail, present to the verification and design teams. Understand the existing complex testbench and update it to add new features. Learn & Implement various coding techniques System Verilog, UVM Qualifications B.Tech or M.Tech Electronics Trained VLSI engineers Exposure to SystemVerilog, UVM, VHDL Good understanding of C, C++,OOP concepts. 0-4 years of experience in DV
Job Title
Design Verification Engineer