Job Title

Senior Principal / Principal IP Design Engineer - High-Speed Interfaces Location- Bangalore About Omni Design Technologies Omni Design Technologies is a leading provider of high-performance, ultra-low power IP cores, from 28nm down through advanced FinFET nodes, which enable differentiated system-on-chip (SoC), in applications ranging from 5G, wireline and optical communications, LiDAR, radar, automotive networking, AI, image sensors, and the internet-of-things (IoT).Our data converter (ADC and DAC) IP cores range from 6-bit to 14-bit resolution and from a few MSPS to more than 100 GSPS sampling rates. Omni Design, founded in 2015 by semiconductor industry veterans, has an excellent track record of innovation and collaboration with customers to enable their success. The company is headquartered in Milpitas, California with additional design centers in Fort Collins-Colorado, Bangalore-India, Hyderabad-India, Dublin-Ireland, Boston-Massachusetts. We are seeking a highly skilled and experienced IP Design Engineer to join our team, focusing on the design, development, and validation of cutting-edge high-speed interface Intellectual Property (IP). The ideal candidate will have a strong background in complex digital and mixed-signal design, with a particular emphasis on interfaces such as UCIe, Die-to-Die (D2D), and various memory PHYs (DDR/LPDDR). Expertise in advanced clocking architectures including PLLs and DLLs is also essential.This role involves contributing to the full IP development lifecycle, from architectural definition and RTL design to silicon validation and post-silicon support, ensuring first- pass silicon success for critical products that enable next-generation data center interconnects.Key Responsibilities: • Design & Development: Architect, design, and implement high-speed interface IPs, including UCIe, D2D, DDR, and LPDDR PHYs. Contribute to the development of high-speed SerDes IP transceivers supporting rates like 100G PAM4 (106.25 Gbps), 50G PAM4 (53.125 Gbps), and 25G NRZ (26.5625 Gbps) for applications such as PCIe, Ethernet, and data center interconnects.• Clocking Design: Develop and optimize PLL (Phase-Locked Loop) and DLL (Delay- Locked Loop) circuits for high-speed clock generation and synchronization, ensuring low jitter and high accuracy. This includes experience with Fractional/Spread-spectrum/Integer Frequency synthesizers, LC VCOs, Multi- Modulus Dividers, Charge Pumps, LPFs, LDO regulators, and BGRs.• IP Development Lifecycle: Participate in the complete IP design flow, including architectural definition, specification development, RTL coding, synthesis, static timing analysis (STA), and collaborating on physical design activities (GDSII). 1 • Verification & Validation: Work closely with verification teams to define test plans, debug complex design issues, and lead pre-silicon and post-silicon validation efforts, including silicon bring-up and characterization .2 Implement features for deep in-cable diagnostics (e.g., eye metric readout, PRBS bit error rate, loopback modes), fleet management, and security for robust interconnect solutions.• Analog/Mixed-Signal Integration: Collaborate on the integration of analog and mixed-signal blocks within the PHYs, addressing complex integration challenges and optimizing for performance, power, and area (PPA).• Documentation: Create comprehensive design specifications, integration guidelines, and application notes for IP blocks.• Problem Solving: Debug and resolve complex design issues at various stages of the development cycle, including silicon debugging and fault isolation.• Standards Compliance: Ensure IP designs comply with industry standards (e.g., JEDEC for DDR/LPDDR, QSFP-DD/OSFP mechanical and common management interface specifications) and customer requirements. • Performance Optimization: Focus on achieving low-latency data paths ( and optimizing for lower power consumption in high-speed interconnect solutions. Required Qualifications: • Bachelor's or Master's degree in Electrical Engineering, Electronics Engineering, or a related field.3 • 10-20 years of experience in digital, mixed-signal, or analog IP design within the semiconductor industry. (Adjust X based on Senior/Principal level). • Proven experience with high-speed interface designs such as UCIe, D2D, DDR PHY, or LPDDR PHY. • Demonstrated experience in the design and optimization of PLLs and/or DLLs, including various types of frequency synthesizers and clock generation circuits. • Familiarity with the entire IP development flow from architectural concept to silicon validation. • Strong understanding of signal integrity, power integrity, and layout considerations for high-speed designs, especially for PAM4 and NRZ signaling over copper cables. • Proficiency with industry-standard EDA tools for design, simulation, and analysis. • Experience with deep diagnostic features, security implementations (firmware security, unauthorized access prevention), and non-disruptive firmware updates for high-speed modules. • Excellent problem-solving skills and attention to detail. • Strong communication and collaboration skills to work effectively with cross- functional teams.Contact: Uday Mulya Technologies muday_bhaskar@ "Mining The Knowledge Community"