Job Title

Principal /Staff Digital Design Engineer About Omni Design Technologies Omni Design Technologies is a leading provider of high-performance, ultra-low power IP cores, from 28nm down through advanced FinFET nodes, which enable differentiated system-on-chip (SoC), in applications ranging from 5G, wireline and optical communications, LiDAR, radar, automotive networking, AI, image sensors, and the internet-of-things (IoT). Our data converter (ADC and DAC) IP cores range from 6-bit to 14-bit resolution and from a few MSPS to more than 100 GSPS sampling rates. Omni Design, founded in 2015 by semiconductor industry veterans, has an excellent track record of innovation and collaboration with customers to enable their success. The company is headquartered in Milpitas, California with additional design centers in Fort Collins-Colorado, Bangalore-India, Hyderabad-India, Dublin-Ireland, Boston-Massachusetts. Principal Digital/RTL IC Design Engineer Bangalore / HyderabadBangalore Engineering – Digital Circuit Design /Principal Digital Design Engineer focusing on the digital datapath of high-performance analog-to-digital and digital-to-analog converters. Job responsibilities include RTL design, verification, behavioral modelling, support and assist with synthesis, timing closure and P&R flow for the digital controller for high performance data converters in cutting edge technologies Qualifications BS/BE/MS/MTech + 5-15 years or equivalent experience in high-performance digital or mixed-signal IC development in advanced CMOS processes Strong foundation in digital design concepts for complex ASICs Hands on experience with the Verilog RTL coding including state machines, adders, multipliers, combinatorial logic, etc Strong understanding of digital design for mixed signal control loops and designing Verilog code to control analog circuits (e.g. digital backend for ADC, digital PLL, etc) Familiarity with behavioral Verilog code, including wreals Ability to write thorough testbenches Preferred knowledge of Genus, Tempus, Modus and other Cadence tool set used for ASIC design flow Excellent understanding of SystemVerilog Knowledge of SystemVerilog assertions preferred Familiarity with place and route tool flow using Innovus preferred but not mandatory Basic understanding of digital signal processing – MATLAB understanding preferred Extensive experience with synthesis flow in nano-meter scale CMOS Extensive experience with place and route flow interface Deep understanding of constraints, especially for mixed-signal designs, including multiple clock domains and clock gating Familiarity with timing closure and static timing analysis tools with the MMMC modes Experience with scan chain vector generation and verification Experience with flow automation through scripting – shell scripts, Makefile, Python or similar languages Familiarity with Cadence Encounter tool flow preferred but not mandatoryWe are looking for trailblazers ...We strongly believe that the pace of the ongoing hardware revolution will be greatly accelerated by Design’s IP cores and the rapidly emerging semiconductor embedded design business ecosystem.we have created an exciting environment with amazing talent across multiple disciplines. We like self-motivated individuals, we encourage initiative, we look for leadership qualities, we value teamwork, we like diversity, and we reward excellence. We are looking for trailblazers to bring our vision to fruition.If you are interested in making an impact as part of a young, fast growing, cutting edge technology company, please reach out to us.We are a equal opportunity employer. We offer excellent compensation. We seek individuals that share our high standards and commitment to excellence.Contact: Uday Mulya Technologies muday_bhaskar@