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Job Title


Senior Design Verification Engineer


Company : Dabster


Location : Udaipur, Rajasthan


Created : 2025-08-01


Job Type : Full Time


Job Description

Work location: NetherlandsSponsorship will be provided.About Us: At Dabster, we specialise in connecting top engineering talent with leading global companies. We are currently seeking an experiencedSubsystem/SOC Integration Senior Engineerto join our client's team. Our goal is to deliver world-class recruitment solutions, helping our clients build the future of semiconductor innovation.Who Will You Work With: Our client is a globally recognised leader in semiconductor design and development, with teams based in Sophia Antipolis, France, and Cambridge, UK. You will work alongside industry experts focused on cutting-edge SoC and subsystem integration for next-generation products.About the Role: As aSubsystem/SOC Integration Senior Engineer , you will contribute to IP integration, RTL development, and design reviews as part of complex SoC and subsystem projects. You will support micro-architecture design, manage IP configurations, implement power intent using proprietary flows, and assist with synthesis and verification activities. This is a 6-month B2B contract with strong potential for extension, and the role is fully remote within the EU or UK, with occasional travel required for face-to-face meetings at client sites.Key Responsibilities: Develop and review micro-architecture based on final requirement specifications. Manage and render IP configurations per design requirements. Perform RTL coding and lead design reviews. Integrate IP at subsystem/SoC level in line with micro-architecture specifications. Implement power intent using customer-specific tools and flows. Support trial synthesis, update constraints, and perform LEC (logical equivalency checking). Provide verification and debug support.Preferred Skills: Strong experience in micro-architecture design and RTL coding using SystemVerilog. Proficient with synthesis tools like Design Compiler or Fusion Compiler. Hands-on experience in SDC (Synopsys Design Constraints) development. Ability to debug LEC failures and perform RTL/gate-level debug using tools such as Verdi. Strong analytical and problem-solving skills in IP and SoC design environments.