3 to 6 year experience in DFT feature verification (such as JTAG, MBIST, SCAN, fuse, IO-PHY loopback testing) • Strong background in Verilog, SystemVerilog (SV), SVA, UVM verification methodologies and C++ • Strong debug skills and experience with debug tools such as Verdi. • Experience with EDA simulation tools like Synopsys VCS, Cadence NCSIM, Verdi • Experience with scripting languages like Tcl/Perl/Ruby/Python • Working knowledge of Unix/Linux OS, file version control. Additional skills: • Experience in ATE debug, Synthesis, formal/LEC, or power analysis will be a plus. • Strong analytical/problem solving skills and pronounced attention to details • Knowledge of STA Constraints for various DFT modes. • Excellent written and verbal communication
Job Title
DFT Engineers 5 years