Job Title

Key Responsibilities: Include the development and preparation of multi-dimensional layouts and detailed drawings of the semiconductor devices from schematics and related geometry provided by design engineering. Working on layout design of owned blocks with Cadence Virtuoso XL. Working on block and top-level level layout verification with Calibre. Extensive PAD Ring and Top/Chip leve l layout experience Working with analog/mixed-signal and digital design teams to ensure proper layout design Block level floor planning and layout IC top level floor planning and area estimation Using recommended layout and verification techniques, tools, and flows to produce optimal designs Generate post-layout extraction Create layout related documentation and conduct layout reviews Interact with packaging team to generate clean bonding diagram that complies with assembly rules Education & Experience : Minimum degree in Electrical/Electronic Engineering or equivalent. At least 6-10 years of relevant working experience. Key Qualifications: Good understanding of package/substrate design and package assembly rules related to flip chip designs, BGA, LFCSP etc. Experience in IO Pads, ESD clamps and Analog Mixed Signal IP layout Layout experience in the following technology nodes is a plus: 180, 40nm and 22nm GF Good team worker with multi-discipline, multi-cultural and multi-site environments Good problem-solving skills are essential where problems are analyzed upfront, identifying gaps, and providing optimum solutions Knowledge in Skill/perl/tcl scripting is a plus.