Job Title

Analog Layout Engineer PositionExperience- 4 to 6 yearsAbout the RoleTechnology Experience: TSMC 16/12nm, 7nm, 5nm, 3nm and below. Experience with other foundries like Intel, Samsung, GF is also acceptable. Preference: TSMC 5nm/3nm experience.Responsibilities- Design and development of critical analog, mixed-signal, custom digital blocks. - Full-chip level integration support. - On-time delivery of block-level layouts with high quality.Qualifications- BE or MTech in Electronics/VLSI Engineering.Required Skills- Strong knowledge of verification flows: LVS, DRC, DFM, Antenna Check, EMIR. - Must have: Cadence VLE/VXL and Mentor Graphics Calibre DRC/LVS.Preferred Skills- Good communication skills for cross-functional collaboration. - Ability to work independently. - Hands-on experience in recent lower nodes is highly desirable. - Experience with HBM and analog blocks like Regulators, Charge Pumps, Power Management is a plus.Pay range and compensation packageNot specified.Equal Opportunity StatementWe are committed to diversity and inclusivity.