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Role Overview: We are looking forSenior ASIC Design Verification Engineerswith strong expertise inSystem Verilog (SV)andUVM methodology . The ideal candidate will have hands-on experience inSoC and IP-level verificationacross multiple domains, along with good scripting skills. Exposure toC languageis a plus.Key Responsibilities: Develop and executeverification plansfor SoC and IP-level designs. Build and maintaintest benchesusingSystem Verilog and UVM . Performfunctional verification , including simulation, coverage analysis, and debugging. Collaborate with design and architecture teams to ensureverification completeness . Automate verification flows usingscripting languages(Python, Perl, Shell, etc.). Analyze and reportcoverage metricsand ensure compliance with verification goals.Required Skills: 4-20 years experience inASIC Design Verification . Strong knowledge ofSystem VerilogandUVM methodology . Hands-on experience inSoCandIP-level verificationacross domains such as: Automotive Audio Networking High-Speed Interfaces(PCIe, Ethernet, USB) Memory Subsystems(DDR, LPDDR) Processor Subsystems(ARM, RISC-V) Proficiency inscripting languages(Python, Perl, Shell). Good understanding ofverification concepts , coverage, and debugging techniques.Good to Have: Exposure toC programmingfor embedded or verification-related tasks. Familiarity withformal verificationandlow-power verificationmethodologies. Experience withindustry-standard EDA tools(Synopsys VCS, Cadence Xcelium, Mentor Questa).Education: Bachelor’s or Master’s degree inElectronics, Electrical, or Computer Engineeringor related field.