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Greetings ! Hiring: Physical Design Engineer Lead – Bangalore (4 Days WFO) Experience Range:13.5–20 Years Industry:Semiconductors / VLSI / ASIC Design Employment Type:Full-Time Job Title: Physical Design Engineer Location: Bengaluru, India Job Summary We are looking for an experiencedPhysical Design Engineerto join our chip development team. You will be responsible for implementing and optimizing the physical layout of complex ASICs fromRTL to GDSII , working closely with RTL, Verification, DFT, and other cross-functional teams to ensure successful tape-out of high-performance, low-power silicon designs. Key Responsibilities Execute physical design tasks includingfloorplanning, power planning, placement, CTS, routing , andphysical verification (LVS/DRC) . Work ontiming closureusing STA tools and fix violations across multiple PVT corners. PerformIR dropandEM analysis , and drive fixes for power integrity. Collaborate withRTL, DFT, packaging, and manufacturingteams. Debug issues acrossPnR, DRC/LVS, and timing flows , providing RCA and solutions. Contribute toflow development, automation , and overall design efficiency improvements. Required Qualifications BE/BTech in Engineering or equivalent. 7+ yearsof experience in ASIC physical design with proven tape-out experience. Strong hands-on expertise with tools such asInnovus, ICC2, PrimeTime, Voltus, Calibre . Solid understanding oftiming, SI, IR drop, physical verification . Good scripting skills inTCL, Python, or Perl . Excellent problem-solving and communication skills. ✨ Preferred Qualifications Experience withhierarchical design methodologies . Exposure tolow-power design (UPF) . Experience withadvanced nodes (7nm, 5nm or below) . Note:For candidates with10+ years experience , expertise in7nm–10nmis required. Work Mode: Bangalore – 4 Days WFO