Job Title

essolve – STA Engineer (4+ Years Experience)Location: BangaloreJob Type: Full-TimeExperience: 4–8 yearsDomain: ASIC / SoC – Static Timing AnalysisJob SummaryTessolve is seeking a skilled STA Engineer with 4+ years of hands-on experience in block-level and/or chip-level timing analysis and closure. The ideal candidate should be proficient with industry-standard timing tools, sign-off methodologies, and timing constraints development for advanced technology nodes.Key ResponsibilitiesStatic Timing Analysis & Closure- Perform block-level and top-level STA using Synopsys PrimeTime or equivalent sign-off tools. - Develop, validate, and maintain timing constraints (SDC) for functional and test modes. - Analyze and resolve setup, hold, DRV, SI/Noise, and cross-corner timing issues. - Drive timing closure by coordinating with RTL, physical design, DFT, and architecture teams.Timing Sign-Off & Debug- Perform multi-mode, multi-corner (MMMC) analysis for all PVT corners. - Support ECO generation and validation for timing fixes (functional & timing ECOs). - Debug clock tree, macro timing, and route-based timing problems. - Run and interpret report timing, report_timing_summary, path-group analysis, etc.Tool & Flow Expertise- Work with Synopsys PrimeTime (PT/PTS), Cadence Tempus, or equivalent STA sign-off tools. - Understand modeling of libraries (LIB), SDF, SPEF, OCV/AOCV/POCV, and latency models. - Support methodology improvements for timing closure and sign-off automation.Required Skills & Experience- 4+ years of hands-on experience in STA for ASIC / SoC projects. - Strong knowledge of: - SDC creation and validation - Setup/Hold analysis and fixes - Noise/SI timing checks - MMMC timing methodologies - OCV, AOCV, POCV modeling - SPEF/SDF/LIB interpretation - Solid understanding of digital design fundamentals, clocking concepts, and physical design interactions. - Hands-on experience with Synopsys PrimeTime (preferred) or Cadence Tempus. - Proficiency with Tcl scripting for automation.