About the Company:We are looking for a seasoned Power-Management/PLL Circuit Engineer to lead the design and development of cutting-edge PMIC and PLL IPs for high-performance SoCs. This role is ideal for someone who thrives on solving complex analog design challenges and driving innovation from concept to silicon.About the Role:Power-Management / PLL Circuit EngineerLocation: Bangalore, Karnataka, IndiaResponsibilities:Lead the architecture, design, and verification of power-management circuits, including voltage regulators, DC-DC converters (PWM/PFM), and advanced LDOs (ultra-low-noise, capless, fast-transient).Design high-performance PLLs for frequency synthesis and low-jitter clock generation.Run detailed simulations, analysis, and modeling to ensure robustness and optimal performance.Collaborate closely with layout teams to guide floor-planning, device matching, and parasitic-aware design.Perform silicon validation, debugging, lab testing, and characterization of PMIC and PLL blocks.Mentor junior engineers and provide strong technical leadership across projects.Contribute to system-level requirements, product definitions, and cross-functional reviews.Qualifications:Bachelor’s or Master’s in Electrical Engineering or related field.10+ years of hands-on experience in power-management and PLL circuit design.Deep expertise in analog/mixed-signal design and power electronics.Strong understanding of control systems, stability analysis, and compensation techniques.Proficiency with industry-standard tools (Cadence, Spectre, etc.).Experience with lab equipment and silicon debug/characterization.Required Skills:Power-management circuit designPLL designAnalog/mixed-signal designControl systemsIndustry-standard tools proficiencyPreferred Skills:Experience with lab equipmentSilicon debug/characterization
Job Title
Engineer