Job Title

#DSP_Senior_Lead_STA_Engineer_Noida.General Summary:As a Senior Lead STA Engineer, you will play a critical role in the design, optimization, verification, and timing closure of advanced hardware platforms. You will collaborate closely with cross-functional teams across design, physical implementation, and verification to ensure best-in-class performance, power efficiency, and quality.Minimum QualificationsEducation & ExperienceBachelor’s degree in Computer Science, Electrical/Electronics Engineering, or a related field 4+ years of hands-on experience in Static Timing Analysis (STA), timing constraints, and physical implementationKey Technical Skills & ExperienceStrong expertise in industry-standard STA tools such as PrimeTime (PT) and TempusFamiliarity with physical design and P&R tools including Innovus and Fusion CompilerProven experience in timing closure and STA fixing, including critical path analysis and clock path debuggingHands-on experience creating and implementing complex ECOs for timing convergence across extensive corner scenarios using:TweakerTempusPhysical PT ECOsManual ECO techniquesExperience with advanced deep sub-micron technology nodes (below 10nm) is strongly preferredKnowledge of high-performance and low-power interface timing is a plusStrong fundamentals in VLSI design, synchronous design principles, timing checks, and constraint developmentProficiency in UNIX/Linux environmentsStrong scripting skills in TCL, PT-TCL, and Tempus-TCLPython scripting experience is an added advantagePLease do reach me on +91-9071106778