Job Title

Job Summary We are seeking a highly skilled Physical Design Engineer to join our VLSI/ASIC design team. The candidate will be responsible for the complete physical design flow, from netlist to GDSII, ensuring high performance, power, and area (PPA) targets while meeting timing and quality requirements. Key Responsibilities Perform end-to-end ASIC Physical Design flow: floorplanning, placement, CTS, routing, and signoff Handle timing closure using static timing analysis (STA) Perform power analysis and optimization Conduct physical verification including DRC, LVS, and ERC Run IR drop and EM analysis Collaborate with RTL, DFT, and signoff teams to resolve design issues Optimize designs for performance, power, and area (PPA) Support ECO implementation and design iterations Ensure designs meet foundry and process guidelines Required Qualifications 3+ Years Experience in Physical Design. Bachelor’s or Master’s degree in Electronics, Electrical Engineering, or related field Strong understanding of VLSI physical design concepts Hands-on experience with PD tools such as: Cadence Innovus / Encounter Synopsys ICC2 Proficiency in STA tools like PrimeTime Experience with advanced technology nodes (e.g., 7nm, 5nm, 3nm is a plus) Good understanding of DRC/LVS rules and signoff flows Scripting skills in TCL, Python, or Perl Preferred Skills Experience with low-power design techniques Knowledge of UPF/CPF Familiarity with DFT concepts Experience working with multi-clock and multi-voltage designs Good debugging and problem-solving skills Soft Skills Strong communication and teamwork skills Ability to work in fast-paced, deadline-driven environments Attention to detail and strong analytical skills