Job Title

MediaTek, Bangalore Backend Integration Engineer (Staff/Senior Staff) KEY RESPONSIBILITIES: Utilize Synthesis tool variables and methodologies to extract the best PPA achievable. (Genus/Fusion Compiler) Analyze critical timing violation groups and congestion – solve them by finetune floorplan or placement constraints. DFT Insertion and debugging basic DFT DRC issues. Interact with Design teams & Physical design teams to get the best synthesis results. Experience in Logic Equivalence Checks Conformal LEC/Formality, Low power Checks (UPF/CLP). OR Responsible for Multi Voltage domain STA environment setup, execution and timing closure Drive the timing checks at pre-layout/placement/pre-CTS/post-CTS/Route stages, debug skew/latency issues and achieve timing signoff. Ensuring timing correlation between PnR STA and timely feedback to PD team Driving SoC level timing Closure. Generating timing ECO using Tweaker/Prime Closure. PREFERRED EXPERIENCE: 5+ years of experience in timing closure of high frequency blocks both from Physical aware Synthesis/Timing Closure perspective (> GHz range) Analyzing the timing reports and identifying both design and constraints related issues. Worked on blocks/SoC with multiple power and voltage domains Preferred EDA tool experience: Primetime, Tweaker/Prime Closure, Genus/Innovus/Fusion Compiler Good Understanding of DFT modes/DFT architecture to debug MMMC timing violations Good understanding of physical design flow and ECO implementation Strong understanding of SDC constraints & AOCV/POCV concepts. Strong TCL/scripting knowledge. Desirable : Strong debugging, analysis/problem solving and presentations skills. Take initiative towards Design/Dataflow Understanding and drive design changes/flow enhancements for faster convergence Interaction with all stake holders which includes weekly status reporting, issue tracking and resolution. Project management experience.