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Hi,We have an opening for DV (Design Verification) - Ethernet - Lead position - BangaloreJD for Design Verification: - 8+years to 12+yrs- Good understanding of verification concepts and techniques. Very good knowledge of Verilog/System Verilog and UVM. - Experience and knowledge in Verification of IP’s related to different applications. Good Knowledge in Power aware verification and Gate level verification is preferable. Should be able to understand the Full-chip Verification requirements as well and good knowledge in industry standard protocols. - Verification for complex IP’s and close the Verification to the challenging milestones. - Strong knowledge of Ethernet, MAC,Please share your profile to Jayalakshmi.r2@ or share your reference.Regards,Jaya