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Job OverviewWe are seeking a Principal Engineer of SD Development who will drive synthesis, APR, timing closure, and verification across advanced technology nodes. This is a high-impact leadership role where technical mastery meets strategic execution.Location: Bangalore, IndiaExperience: 15+ yearsKey Responsibilities:Strategic Leadership- Define and evolve methodologies for IP-level back-end execution, ensuring scalability across multiple projects. - Act as the technical authority for synthesis, APR, STA, and sign-off flows. - Partner with front-end design, verification, and DFT teams to align execution with overall design goals.Execution Excellence- Lead the complete back-end flow from RTL to GDSII, ensuring delivery of high-quality IPs. - Drive timing closure across multiple corners/modes, managing ECO cycles with precision. - Oversee floorplanning, placement, routing, and optimization to achieve aggressive PPA (Power, Performance, Area) targets. - Deliver robust Mixed-Signal IPs in domains including:Power Delivery (regulators, distribution networks)- Voltage Regulators (VRs) - UCIe (Universal Chiplet Interconnect Express) for advanced packaging and connectivity - Memory IPs (SRAM, DRAM interfaces, controllers) - Sensor IPs (mixed-signal integration for sensing applications)Innovation & Optimization- Introduce automation and flow improvements to reduce cycle time and enhance predictability. - Evaluate emerging EDA tools and methodologies, ensuring the team stays ahead of industry trends. - Champion best practices in physical design, verification, and sign-off.Team Development- Mentor engineers, fostering technical growth and leadership readiness. - Build a culture of accountability, collaboration, and continuous improvement. - Provide technical reviews, feedback, and guidance to ensure execution quality.Experience: 12–18 years in semiconductor back-end design, with at least 5 years in leadership roles.Technical Expertise:- Hands-on with APR tools (Synopsys ICC2, Cadence Innovus, or equivalent). - Strong knowledge of synthesis, STA, timing ECOs, and sign-off flows. - Familiarity with power analysis, IR drop, EM, and physical verification (DRC/LVS). - Proven track record in delivering Mixed-Signal IPs across power, memory, interconnect, and sensor domains. - Leadership Skills: Proven ability to lead cross-functional teams, manage stakeholders, and deliver IPs on schedule. - Soft Skills: Exceptional communication, problem-solving, and decision-making abilities.Preferred Experience- Successful tape-outs at advanced nodes (5nm, 3nm, or below). - Experience with chiplet architectures and integration using UCIe. - Deep understanding of mixed-signal verification flows and co-simulation methodologies. - Familiarity with low-power design techniques, multi-voltage domains, and power integrity analysis. - Hands-on experience with memory IP integration (SRAM/DRAM controllers, high-speed interfaces). - Exposure to sensor IP design and integration in mixed-signal environments. - Strong background in ECO implementation and closure across multiple corners/modes. - Prior leadership in global, cross-site execution teams.Please reach out to varun@