Job Title

Job Title: Verification EngineerWork Location: HyderabadExperience: 5+ YearsNotice Period: Immediate (Max 15 Days)Job Description:We are looking for a Verification Engineer to work on IP-level functional and performance verification using a UVM-based environment. The role involves integrating SystemC models into UVM, performing functional and performance correlation with RTL, and debugging issues to support timely delivery of RTL-aligned models.Required Skills- 5+ years of experience in UVM based IP-level verification. - Strong hands-on expertise in: - SystemVerilog and UVM methodology - RTL verification and debugging - Solid understanding of digital design concepts and verification methodologies. - Excellent communication and collaboration skills. - Ownership mindset with a focus on quality and timely delivery.Preferred Skills- Experience with NOC Subsystem - Good Knowledge of Memory Protocols DDR, LPDDR, HBM - SystemC/TLM modeling concepts - Experience with SystemC–RTL co-simulation setups. - Knowledge of profiling and performance analysis techniques. - Exposure to C++ modeling and high-level performance models. - Experience with scripting languages (Python, Perl, Shell) for automation.QualificationB.E/M.E/M.Tech or B.S/M.S in EE/CE