Job Title

Role OverviewWe are seeking a visionary Principal Engineer, Chip Design Lead to join our client’s premier SoC development team. This role involves driving the chip RTL design for power efficient chips and collaborating across architecture, verification, and physical design teams to deliver world-class semiconductor solutions.Location: [Hyderabad / Hybrid]Experience: 10+ YearsKey Responsibilities- Actively drive the chip integration and the team to meet the project goals - Review architecture specifications, create RTL micro-arch specifications and drive the RTL design using Verilog/SystemVerilog and industry-standard methodologies - Optimize RTL for timing, power, and area targets while ensuring design scalability - Work closely with architecture, Verification, firmware, and physical design teams during development and implementation to achieve the design targets - Collaborate with verification teams to ensure functional correctness and coverage goals • Work closely with synthesis and physical design teams for PPA analysis and design convergence - Work with DFT teams to achieve coverage goals - Contribute to methodology improvements for design implementation and timing closure • Provide technical leadership and guidance to junior engineers - Provide support to functional validation teams in post silicon debug • Collaborate with other functional teams including Verification, Validation, DFT, physical design and emulation teams to achieve project targets - P selection and make/buy decisionsRequired Qualifications & SkillsEducation & Experience- BTech/MTech in Electrical/Electronic Engineering, Computer Engineering or Computer Science with 15+ years of hardware design experience - 10 years of experience in RTL design at IP and chip level - Prior experience with CPU based chip designs is a must - Experience in D2D protocols like UCIe or Bunch-of-wires - Experience in Design of Microcontroller and Microprocessor chips, CPU cores, Interconnect, Peripherals - Proven track record in timing closure and physically aware design flows - Strong communication skills (written and verbal), problem solving, teamwork, attention to detail, commitment to task, and quality focus - Strong understanding of synthesis, STA, and power optimization techniques - Experience with low-power design techniques and multi-clock domain architectures - Experience in protocols like AHB/AXI/CHI, Memory (ROM, RAM, Flash, LPDDR/DDR3/4) and memory controllers - Strong domain knowledge of clocking, system modes, power management, debug, security and other domains - Experience in more than one of Chiplets / Interconnect / CPU / NPU / GPU / Imaging / Display / Memory controller / Debug / clocking and reset design - Prior experience with any of these would be a plus: High Speed Peripherals like DDR, PCIe, Ethernet, GPU, VPU (Video Processing Unit); NIC/FlexNOC interconnect; Flash memory subsystems. - Strong drive & ability to coordinate work across highly experienced global team.If you are open to exploring this opportunity, please apply and share your resume to Heena (/in/heena-kausar-3a2b94a4) at heena.k@