Job Title

We are looking for an experienced Senior Architecture Leader to define and drive next-generation MCU chiplet architectures and Die-to-Die (D2D) interface IPs. This role offers a chance to work at the intersection of system architecture, microarchitecture, and cross-functional execution. Key ResponsibilitiesDefine and drive chiplet architecture optimized for MCU constraintsLead architecture of D2D interface IPs (UCIe / Bunch-of-Wire)Collaborate closely with product and software architectsShape microarchitecture of IP blocks and subsystemsWork with verification teams on test-plan development and reviewsCollaborate with Design, Validation, DFT, Physical Design, and Emulation teamsSupport post-silicon debug and functional validationDrive IP selection and make/buy decisions Qualifications & ExperienceBTech / MTech in EE / ECE / Computer Engineering / Computer Science15+ years of hands-on hardware architecture experienceStrong communication, problem-solving, and teamwork skillsExperience with D2D protocols (UCIe, Bunch-of-Wire)Expertise in MCU/Microprocessor architecture, interconnects, cache coherencyExperience benchmarking and tuning IP/SoC performanceStrong knowledge of AHB/AXI/CHI, memory systems (ROM, RAM, Flash, LPDDR/DDR3/4)Deep understanding of clocking, power management, system modes, debug, security Good to HaveNIC / FlexNOC interconnect experienceFlash memory subsystemsPower management architectureVirtual Prototyping tools: ARM Fast Models, Synopsys Virtualizer, Wind River SIMICS What We’re Looking ForA can-do attitude and openness to diverse teams and culturesPassion for building scalable, high-performance architectures