Job Title

Job Title:Analog Layout Engineer – Advanced / Lower Nodes (TSMC)Experience:4 -7 YearsLocation: Hyderabad (F2F) Job SummaryWe are seeking an experienced Analog Layout Engineer to design and implement high-performance analog and mixed-signal IC layouts in advanced CMOS technology nodes (e.g., 28nm, 16nm, 7nm, 5nm, 3nm) at TSMC. The role requires close collaboration with analog design, verification, and foundry teams to ensure robust, manufacturable, and high-yield layouts.Key ResponsibilitiesDesign and deliver full-custom analog and mixed-signal layouts for advanced TSMC technology nodesHandle layout of blocks such as LDOs, PLLs, ADC/DACs, SerDes, amplifiers, bandgaps, clocking, and IOsApply advanced layout techniques:Matching, symmetry, common-centroid, interdigitationGuard rings, shielding, substrate isolationEM/IR-aware routing and reliability-driven layoutEnsure compliance with TSMC DRC/LVS/DFM rules, including advanced node-specific constraintsAddress parasitics, coupling, noise, and variability challenges in lower nodesPerform PEX extraction and support post-layout simulation and silicon debugWork closely with analog designers to optimize layout for performance, yield, and reliabilityInteract with TSMC foundry teams for rule clarifications, waivers, and silicon issuesRequired QualificationsBachelor’s or Master’s degree in Electrical Engineering or related field5+ years of hands-on analog layout experience (less for junior roles)Strong experience in TSMC advanced nodes (≤28nm preferred)Expertise with Cadence Virtuoso layout environmentSolid understanding of device physics, matching, and layout-dependent effects (LDE)Proven ability to handle complex DRC and advanced node constraintsPreferred QualificationsExperience with FinFET nodes (16nm/7nm/5nm/3nm)Familiarity with EM/IR, antenna rules, and reliability analysisExperience in high-speed or low-noise analog designsTape-out experience on multiple TSMC advanced nodesKnowledge of DFM, yield enhancement, and silicon correlation