Job Title: Senior Physical Verification EngineerExperience: 5+ YearsLocation: BengaluruEmployment Type: Full-TimeJob DescriptionWe are seeking a Senior Physical Verification Engineer with 5+ years of hands-on experience in physical verification for advanced ASIC/SoC designs. The ideal candidate will have strong expertise in DRC, LVS, ERC, and sign-off verification, with the ability to drive clean tape-outs and collaborate across design teams.Key ResponsibilitiesPerform Physical Verification sign-off including DRC, LVS, ERC, and Antenna checksDebug and resolve complex PV violations across block and full-chip levelsWork closely with Physical Design, Foundry, and CAD teams to close verification issuesDevelop and maintain PV runsets, rule decks, and verification flowsPerform DFM and density checks to ensure manufacturabilityAnalyze and support tape-out readiness and final GDS sign-offAutomate verification flows using TCL / Python / PerlProvide guidance and technical mentoring to junior engineersRequired Skills & Qualifications5+ years of experience in Physical Verification for ASIC/SoC designsStrong hands-on experience with Mentor Calibre (DRC, LVS, PERC, DFM)Good understanding of foundry rule decks and advanced technology nodesExperience with hierarchical verification and large-scale designsSolid knowledge of GDSII, LEF/DEF, PDK, and tech filesStrong debugging and problem-solving skillsAbility to work independently and drive closurePreferred QualificationsExperience with advanced nodes (7nm / 5nm / 3nm)Knowledge of low-power verification and ESD/Latch-up checksExposure to physical design or STA flowsExperience with multi-foundry tape-outsEducationBachelor’s or Master’s degree in Electronics & Communication Engineering, Electrical Engineering, VLSI, Microelectronics, or a related fieldM.Tech / MS in VLSI or Microelectronics is a plus
Job Title
Senior Physical Verification Engineer