Job Title

Company: Eteros Technologies India Private LimitedEteros Technologies, Inc. is a Semiconductor Engineering services startup, head quartered in the heart of the Silicon Valley, San Jose, CA, USA. Eteros Technologies India Pvt Ltd is a wholly owned subsidiary offices in Bangalore, Hyderabad and Ahmedabad.Our engineers work on cutting edge technology nodes while working on the state-of-the art designs in the AI/ML, Datacenter, Automotive and 5G domains. ----------------------------------------------------------------------------We are looking for a DFT Lead/Principal Engineer with strong expertise in DFT implementation for complex SoCs. This is a hands-on leadership role where you will own DFT architecture, methodologies, and execution for advanced technology nodes.Location: Bangalore/Hyderabad/AhmedabadExperience Level: 10+ Years-----------------------------------------------------------------------------SummaryMinimum 10yrs+ experience in DFT implementationMust have worked on Scan Insertion, MBiST, ATPG, SimulationsMust have experience with Synopsys DFT tools & FlowsExperience in DFT timing closure preferredExperience in multi-die HBM/Memory testing with Synopsys tools preferredWork hands-on on critical tasks of DFT implementationOwn the DFT implementation flows, methodologies and execution of SoCs ExperienceExperience in all phases of the DFT pre and post-Si for large SoCsImplement DFT of SoC/Full-chip-level and/or high-speed cores/blocksExperience in high-speed, low-power, mixed-signal SoC’s is a plusPreferably worked on 5nm/7nm/12nm/14nm/16nm nodes at the major foundriesExperience in developing DFT architecture, Test-plan, implementation methodologiesExperience in scan insertion, memory-BIST, JTAG/IJTAG, CTL, IEEE 1149.1/1500 wrappers, BSCAN, Compression, ATPG, Simulations, post-Si testing/debugExperience in manual test-point insertion, improve coverage targets, high-compressionExperience in hierarchical ATPG, OCC/OPCG, power-aware scan/ATPG methodologiesExperience in test-mode constraints generation and test-mode timing closureExperience in patter generation for foundry, post-Si support/debugThorough understanding of digital design, timing analysis, and physical design processEDA Tools: Cadence (Encounter-Test, Modus-DFT, Tempus, Conformal), Mentor (Tessent tool suite), Synopsys (DFTC, Tetramax, TestMax-DFT, SMS, PTSI)Requirements• BTech/MTech/PhD with in Electrical or Computer engineering• 10-17years of hands-on experience with DFT and test flow with commercial EDA tools for large and complex SOCs• Strong fundamental knowledge of DFT techniques include JTAG, ATPG, yield learning, logic diagnosis, Scan compression, IEEE 1500 Std. and MBIST• Experience with Cadence & Synopsys DFT tools is required.• Strong programming skills in Perl/TCL/C++ and shell scripting is required• Must be able to solve complex problems and independently drive tasks to completion in a timely manner.• Be able to work under limited supervision and take complete accountability.• Excellent written and verbal communication skills What's in it for you• Work on leading edge technologies• An opportunity for career development and growth• Competitive compensation• Medical Benefits and more