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Job Title


Principal CAD HW/Design/DV Engineer


Company : Tsavorite Scalable Intelligence


Location : Bangalore, Karnataka


Created : 2026-02-17


Job Type : Full Time


Job Description

BangaloreFounded in 2023,by Industry veterans HQ in California,US Location: Greater Bengaluru Area Company DescriptionWe are looking for exceptional talent and leadership to join , the world’s first company developing Agentic Silicon for powering the future of AI.Founded in 2023, our team consists of 90+ highly skilled engineers from leading companies such as Intel, Marvell, Nvidia, Qualcomm, Cisco, AMD, Apple etc. We have deep customer engagements across America, Europe, and Asia, and demonstrated functional prototypes to prove our concept and vision.Principal CAD HW/Design/DV Engineer [Experience Level 10+]We are looking for a CAD Hardware Engineer with strong RTL Design and Design Verification expertise to own and scale verification infrastructure across simulation and emulation environments. This role is critical to ensuring tool flow stability, performance, and release readiness for large-scale hardware programs. The engineer will work closely with RTL/DV teams and EDA vendors to drive productivity, reliability, and continuous improvement. Key ResponsibilitiesOwn and maintain verification infrastructure sanity across RTL, DV, firmware, and system-level flowsMonitor and debug daily simulation and emulation regressions, ensuring rapid triage and resolutionManage release tagging, build readiness, and flow signoff supportPartner with EDA vendor to improve compile time, run time, and tool performanceOwn and maintain Makefiles, build systems, and regression automationMaintain and optimize testlists, regression configurations, and execution strategiesMaintain firmware sanity testing and integration with verification environmentsManage Git repositories, CI/CD pipelines, and verification automation workflowsProactively monitor and manage disk usage and storage resources to ensure uninterrupted regressionsRequired QualificationsBachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or related fieldStrong experience in RTL design and/or Design VerificationHands-on experience with simulation and emulation tool flowsProficiency with Makefiles, scripting (Python/Perl/Bash/Tcl), and automationSolid experience with Git, branching, release management, and CI/CD systemsProven ability to manage large-scale regressions and complex verification environmentsPreferred ExperienceDirect experience working with Siemens EDA toolsFamiliarity with UVM-based verification methodologiesExperience supporting firmware bring-up and FW sanity flowsExposure to compute farm and resource management environmentsCore CompetenciesVerification Infrastructure • CAD Tool Flows • Regression Management • CI/CD Automation • EDA Performance Optimization • Build & Release Engineering • Resource & Disk ManagementContact:UdayMulya Technologiesmuday_bhaskar@/"Mining The Knowledge Community/"